In recent years, digital technologies have remarkably advanced, and there is an increasing demand for an improvement of power consumption, processing speed and precision of an AD converter that converts an analog signal into a digital signal. As a technique that allows an AD converter to operate at high speed with low power consumption, a time interleaving scheme, in which a plurality (M number) of AD converting units are arranged in parallel with each other and sequentially made to convert an analog signal into a digital signal in a time-division manner, is attracting attention.
If the M number of AD converting units having a sampling frequency of fs sequentially operate, the time-interleaved AD converter is equivalent to an AD converter having a sampling frequency of fs×M. Thus, an AD converter having a high sampling frequency can be provided by low-power AD converting units.
With the time-interleaved AD converter, a mismatch in characteristics among the plurality of AD converting units arranged in parallel with each other leads to an unwanted wave component (spurious) or error, resulting in a degradation of AD conversion characteristics. In particular, a degradation in AD conversion characteristics (in particular, an increase of unwanted wave components induced by an offset occurring between the input and the output (referred to simply as an offset hereinafter)) induced by a random error of element characteristics (a threshold voltage of a transistor, a resistance, a capacitance or the like) of individual AD converting units leads to a considerable degradation of change precision characteristics of the entire AD converter and therefore urgently needs to be improved.
A conventional AD converter reduces such offset-induced unwanted wave components by increasing the element size of the AD converting units. For example, if the element size is increased by a factor of four, the offset-induced unwanted wave components can be theoretically reduced approximately to half (=1/√4). However, if the element size is increased, a problem arises that the footprint of the entire chip also increases.